1. Field of the Invention
The invention relates to a memory cell, and more particularly to a partial vertical memory cell of a DRAM and a method of fabricating the same.
2. Description of the Related Art
There is much interest in reducing the size of individual semiconductor devices to increase their density on an integrated circuit (IC) chip. This reduces size and power consumption of the chip, and allows faster operation. In order to achieve a memory cell of minimum size, the gate length in a conventional transistor must be reduced to decrease the lateral dimension of the memory cell. However, the shorter gate length results in higher leakage current that cannot be tolerated, and the voltage on the bit line must therefore also be scaled down. This reduces the charges stored on a storage capacitor, thus requiring a larger capacitance to ensure that stored charges are detected accurately.
FIGS. 1a to 1e are cross-sections of the conventional method of forming a horizontal memory cell.
In FIG. 1a, a silicon substrate 101 is provided. A gate dielectric layer 102, such as gate oxide layer, a conducting layer 103, such as doped poly layer or doped epi-silicon layer, and a patterned mask layer 104, such as nitride layer or photoresist layer, are sequentially formed on the silicon substrate 101.
In FIG. 1b, the conducting layer 103 and gate dielectric layer 102 are anisotropically etched using the patterned mask layer 104 to form a conducting layer 103a acting as a gate and a gate dielectric layer 102a. 
In FIG. 1c, a liner layer 105, such as oxide layer, and an insulating layer 106, such as nitride layer, are conformally formed on the silicon substrate 101, the conducting layer 103a, and the exposed gate dielectric layer 102a. 
In FIG. 1d, the liner layer 105 and the insulating layer 106 are anisotropically etched to form a spacer 106a and a liner layer 105a. 
In FIG. 1e, the silicon substrate 101 is doped to form a Source/Drain (S/D) region beside the conducting layer 103a. A silicide layer 107 is formed on the conducting layer 103a and the S/D respectively.
As the gate size of the MOSFET decreases, a drive current and effect of the gate are difficult to keep high at a low operating voltage.